Constraint-Driven High-Density-Interconnect Design Flow for PCB
Portable Design News, Monday August 18, 2008
With BGAs rapidly approaching 2000 pins and 0.8 mm pin pitch, the era of complex high-density interconnect (HDI) stackups in PCBs is upon us. Laying out a PCB of that complexity—especially if you include 2.4 GHz RF components—is beyond the capacity of most PCB design software.
Cadence Design Systems has just announced a sweeping set of improvements to the Cadence Allegro and OrCAD families of products aimed at boosting performance and productivity through new features and functionality. Part of the Cadence SPB 16.2 release, the new technology helps deliver shorter, more predictable design cycles for PCB designs. With significant improvements for designers using high-density interconnect (HDI), the technology will be of particular value to customers in the high-end consumer electronics market, as well as those in segments such as computing and networking, where users are seeking a constraint-driven HDI design flow.
According to Hemant Shah, Product Marketing Director for Allegro PCB Products, Cadence introduced a constraint-drive design flow in 2000, but used it initially for back-end functions. Cadence then migrated it to the front end to enable engineers to insert their design intent into the tool flow. Shah says the new technology combines manufacturing-aware data with wide range of user-defined HDI design rules, automating the PCB design process while still providing real-time feedback on the constraints. Shah tells Portable Design that Allegro PCB SI will now provide an IBIS 5.0-compliant algorithmic modeling interface for fast and accurate simulation of high-speed serial links.
New technology introduced in Allegro PCB for HDI designs includes new objects, an extensive set of new rules for micro-vias, an enhanced via-transition use model, and changes to the entire PCB design flow to enable a comprehensive constraint-driven HDI design flow. Design partitioning has been enhanced with new capabilities for partitioning the design horizontally and adding soft boundaries to allow users to work in parallel more efficiently, further shortening the design cycle.
Customers can shorten their time to market and reduce development costs for high-frequency signals such as those found in PCI Express 2.0, Serial ATA II, SAS II. Using Allegro PCB SI users can quickly and accurately simulate and validate for BER compliance using new and advanced eye mask capabilities, high-frequency field solver technology. In addition, Allegro PCB SI provides simulation support for interoperable, multi-vendor IBIS 5.0 AMI-compliant transceivers.
With the layout-driven RF PCB design capability introduced in the new release, users can eliminate the need to manually update schematics for RF circuit elements added into the layout. Combined with an improved bi-directional integration with Agilent’s ADS environment, the Allegro PCB RF option allows users to shorten time to create mixed-signal digital-analog-RF designs.
Finally, engineers can specify and embed physical and spacing constraints for critical high-speed nets in the design to improve chances of first-time success while eliminating traditional error-prone verbal, email and spreadsheet-based communication. This can help shorten design cycles and eliminate unnecessary iterations between hardware designers and PCB layout designers.
SPB 16.2 will be available in Q4 2008.
Cadence Design Systems Inc, San Jose, CA (408) 943-1234 [http://www.cadence.com/]
