Virage Logic Delivers Open RTL-to-Test-Floor Embedded Memory Test and Repair Subsystem
Portable Design News, Thursday June 05, 2008
Virage Logic has announced the availability of a completely open register transfer level (RTL)-to-test-floor embedded memory test and repair subsystem based on the latest release of its flagship Self-Test and Repair (STAR) Memory System and the recently introduced STAR Yield Accelerator. The new release of the STAR Memory System features an open memory interface, giving System-on-Chip (SoC) designers the freedom to use the system’s capabilities with their choice of Virage Logic memories, other commercially available third-party memories or internally developed embedded memories.
The STAR Memory System, when used in conjunction with the STAR Yield Accelerator, provides a complete RTL to test floor embedded memory test and repair solution that addresses the needs of SoC designers, test and product engineers. Created to reduce time-to-tapeout and accelerate time-to-volume, the STAR Yield Accelerator bridges the design and manufacturing disciplines to enable automated test vector generation, silicon debug, fault isolation and classification to be used at the critical semiconductor characterization, bring-up, volume manufacturing and electrical failure analysis stages. 
The STAR Memory System provides an integrated, cost-effective solution for embedding on-chip test and repair of memories in designs with a few to a few-thousand memory instances. Repairable or non-repairable embedded memories across any foundry or process node can be incorporated as part of the STAR Memory System to address a broad range of SoC design requirements. The STAR Memory System consists of a complete solution allowing users to select and automatically integrate and verify all of the components required within the system. The STAR Shared Fuse Processor allows users to reduce routing complexity and drastically reduce fuse area, while the STAR Builder automated integration tool enables users to better meet aggressive time-to-volume requirements.
The test floor component of Virage Logic’s complete solution, STAR Yield Accelerator, addresses the requirement to rapidly, cost effectively and accurately identify, analyze, isolate and classify memory faults as designs are readied for transition from first silicon to volume manufacturing. The STAR Yield Accelerator consists of the STAR Verifier, STAR Vector Generator and STAR Debugger components. Leveraging the infrastructure of the STAR Memory System, the STAR Yield Accelerator automatically generates vectors for test equipment and provides fault analysis and root-cause failure guidance based on silicon test results. Using STAR Yield Accelerator, test and product engineers can rapidly analyze failures manifested in embedded memories and inspect the physical location and class of each fault to determine the root cause without involving the IP vendor or SoC designer.
Working in concert to provide a complete RTL to test floor embedded memory test and repair solution, the STAR Memory System is proven to reduce tapeout schedules for new complex SoCs by weeks and the STAR Yield Accelerator can reduce silicon bring-up by months, reducing overall time-to-volume production.
The newest release of Virage Logic’s STAR Memory System, supporting Virage Logic, third-party and internally developed memories, is now available and can be licensed on a project basis with pricing starting at $25,000. STAR Yield Accelerator is also available today. Project-based engagements include software and services with pricing starting at $50,000.
Virage Logic Corporation, Fremont, CA (510) 360-8000 [www.viragelogic.com]
