No end in sight to flash memory growth
Few markets have seen such dramatic changes over the past decade as flash memory.
Samuel Nakhimovsky — Silicon Storage Technology Few markets have seen such dramatic changes over the past decade as flash memory. Invented in the mid-1980s, flash memory use has experienced a rapid growth from niche military applications to practically every consumer, communication, and computing platform in our sight.
Over the past 20+ years, two dominant flash architectures emerged: NOR and NAND. NOR-type achieved early market acceptance for its simple, EPROM-like interface, low power, and fast read access time. As flash memory became more widely accepted, NOR-type flash became the preferred architecture for code storage applications requiring fast and random data read.
At the same time, the NAND-type flash, while offering inherently lower cost per bit than NOR and significantly faster sequential data writes, was relegated to data storage in Flash cards. The NAND interface was too complicated to overcome for chipset designers and required substantial computing power to manage the inherent defects of the NAND devices.
From the end application side, code and data storage needs were so different that NOR and NAND types never truly competed for the same design platform and peacefully coexisted in their respective markets. Since NAND flash mainly competed with hard disk drives in the data storage world, NAND market potential was limited and was well serviced by two of the largest semiconductor companies-Samsung and Toshiba, whose devices were almost identical in architecture, command interface, packaging, etc. So, for a long time any NAND controller that supported one supplier memory could be considered supporting the other supplier’s devices by default.
As the memory industry raced at the speed of Moore’s law, technological and architectural changes had to occur to produce the next generation of NAND products. At the 1-Gbit device milestone, a conventional 512-byte programming page architecture was not optimized for performance and manufacturing. Subsequently, the page size of the higher-density memory was increased fourfold to 2 kB, causing a great degree of incompatibility with existing NAND controllers.
In addition, a new, revolutionary flash technology, multilevel cell (MLC), was introduced to the market. MLC reduces the cost of the same memory density by almost half. While the cost savings makes MLC very attractive for high-volume applications, this memory comes with a price, including longer programming time and higher error rates.
The rapidly shrinking cost of NAND memory did not go unnoticed by the high-tech industry with newer applications seeking to take advantage of this relatively low-cost storage. The distinct boundary of the past between code and data storage is being morphed through integration of previously disparate products and functions into more highly integrated consumer platforms, with some using NAND flash for both code and data storage.
Today, many memory suppliers are seeing this growth potential and are rushing to deliver NAND products to fulfill the insatiable storage needs of the new generation of consumer products. While in the past there was a great deal of uniformity in NAND product architecture, the technological challenges and additional product differentiation through novel features offered by the new entrants make universal support extremely difficult.
With the greater variety of NAND choices, the memory interface designer must consider the differences in program and erase time, block and sector architecture, vendor-specific commands for performance improvements, and other unique features in addition to an already complicated NAND flash interface.
NAND controller suppliers, such as SST, offer users a transparent interface from the host controller to NAND flash through an industry-standard bus eliminating memory interface complexities. In addition, a dedicated NAND controller is specifically tuned to maximize performance and offer support for the widening variety of NAND flash devices on the market.
As the future will surely bring more competitors into the NAND flash field and the rapid pace of technological innovation will introduce disruptive architectural changes, the benefit of dedicated NAND controllers will continue to be more evident.
Already we can foresee new 4-bit-per-cell MLC NAND technology, 4-kB program page size, and greater than 4-bit error correction requirement. With the predicted growth trends, NAND flash will become the dominant product for high-density storage applications, and therefore the use of specialized NAND controllers will be pertinent to achieving high levels of performance and integration with minimal cost impact. PD
Samuel Nakhimovsky is senior product marketing manager in the Application Specific Controller Products Group at Silicon Storage Technology (SST) Inc. (Sunnyvale, CA).
